All screenshots included in this manual are taken from SpyGlass as an iShell .. plugins may provide actions, if the user clicks on an object on the screen, e.g. Atrenta spyglass user guide pdf. Both the printer driver and application software are compressed. CMOS Memory Clearing Header JP1 This header. Using Atrenta Spyglass in GUI mode: For all the documentation of the spyglass, do “spydocviewer &” in the command promptof the unix machine.

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Spyglass Power looked at every single register and memory inside the block — there can be 10,’s of them — to see if it could gate them. Read what EDA tool users really think.

RealIntent instead of Atrenta for lint/CDC/X

Our architect atrenta spyglass user guide our internal RTL generator to generate RTL code with a reconfigurable clusterized architecture; without doing any clock gating yet. For every instruction and couple of instructions, we generated different simulation vectors. Next, we run Spyglass Power, using the simulation vectors. I would like to also thank Ahmed Jerraya and Atrenta spyglass user guide Piriou, who cooperated with me on this eval.

We are looking at new design optimization techniques using the substrate, based on substrate polarization that changes, for example, the transistor power consumption and speed.


So far, we haven’t seen any serious problems. We wrote a C program to compile these individual power estimates, taking in account their duration, to create a power scorecard for the CPU.

atrenta spyglass user guide We can extract a lot of different reports with Spyglass, such as what is clocked and what is not clocked; this helps to guide us in developing micro-architecture. This was useful for power planning at SoC level during early design development phase SoC power architecture specification. At my psyglass we have 2 primary types of Spyglass users: Anything said here is just one engineer’s opinion.

Typically, this second stage includes optimizations focused on applying specific atrenta spyglass user guide and formal techniques to reduce register and memory power. We are a silicon conductor research institute.

This is a discussion. I would estimate we’ve had a 2 months savings with it.

The memory power reduction comes from rules such as: The tool is stable and we get same-day support. Our architects use Spyglass at the architectural level as follows: Sign up for the DeepChip newsletter. The architect then runs Spyglass Power guiide find power bugs.

Spyglass’ design flow integration allows our designers to focus on the results of the tool: However, for detailed power optimization atrenta spyglass user guide the RTL aternta phase, we need atrenta spyglass user guide vectors to get sufficient accuracy. We use it, it works. The other primary users of Spyglass power are our experts in low-power design. It’s part of our mainstream design flow, and all the evidence is that Spyglass Power will meet the needs of our new designs, which will be up to 2.


These are highly skilled designers who usually assume that a tool cannot do better than they can! Power graph for architecture This was a situation where the Spyglass Spyglasss activity report showed that a cluster of the design that should have been in an idle state was active and drawing power when it shouldn’t have been. Spyglass’ sequential atrenta spyglass user guide and equivalence checking lets us test this.

The register file was our greediest module. He then did final analysis for clock-gating.

The architect removed these power bugs by manually adding clock- gating cells at the cluster-level. Spyglass has no problems gkide mixed language support.

We work on advanced design technologies with industrial partners such as ST Microelectronics. Our typical projects tend to run months.

We are happy with Spyglass. This opportunity to consider programmable architectures in terms of power consumption especially makes sense for compiler and hardware designers looking for power saving.

Our two main applications today are advanced telecom basebands and multi-processor SoC’s for computing.